FPGA verilog 提问帖任何问题可以来这里提

你不会也是至芯科技的吧？？

帮我看看，刚学，讲一讲

[source lang="verilog"]
//状态机模块
module sta_machine(clk_div, rst_n, hum_or_car, led_0, led_1);
input clk_div, rst_n;
input hum_or_car; //一个信号表示有或者车
output reg [1:0] led_0, led_1; //led_0表示主干道，led_1表示从干道，高位为绿灯，低位为红灯
reg blink; //blink用来控制灯的闪烁
reg [3:0] cnt; //对灯亮的时间进行计数
reg cnt_clr; //计数器清零的标志，低电平有效
reg [2:0] cs, ns; //cs表示现态，ns表示次态
localparam s0 = 3'b000, s1 = 3'b001, s2 = 3'b011, s3 = 3'b010, s4= 3'b110, s5 = 3'b101;
//描述状态机的现态
always @ (posedge clk_div or negedge rst_n) begin
if(!rst_n) begin
cs <= s0;
cnt <= 0;
end
else begin
cs <= ns;
if(!cnt_clr) cnt <= 0;
else cnt <= cnt + 1;
end
end
//描述状态机的次态
always @ (cs or hum_or_car or rst_n) begin
if(!rst_n) begin
ns = s0;
cnt_clr = 0;
end
else begin
case(cs)
//主路绿灯保持10秒以上且支路有车或行人则进入下一个状态(计数器清零)，否则保持状态
s0: begin
if((cnt >= 4'd10) && (hum_or_car == 1)) begin
ns = s1;
cnt_clr = 0;
end
else begin
ns = s0;
cnt_clr = 1;
end
end
//主路绿灯闪烁3秒后进入下一个状态(计数器清零)，否则保持状态
s1: begin
if(cnt >= 4'd3) begin
ns = s2;
cnt_clr = 0;
end
else begin
ns = s1;
cnt_clr = 1;
end
end
//主路支路均为红灯保持3秒后进入下一个状态(计数器清零)，否则保持状态
s2: begin
if(cnt >= 4'd3) begin
ns = s3;
cnt_clr = 0;
end
else begin
ns = s2;
cnt_clr = 1;
end
end
//支路绿灯主路红灯保持5秒后进入下一个状态(计数器清零),否则保持状态
s3: begin
if(cnt >= 4'd5) begin
ns = s4;
cnt_clr = 0;
end
else begin
ns = s3;
cnt_clr = 1;
end
end
//支路绿灯闪烁3秒后进入下一个状态(计数器清零),否则保持状态
s4: begin
if(cnt >= 4'd3) begin
ns = s5;
cnt_clr = 0;
end
else begin
ns = s4;
cnt_clr = 1;
end
end
//主路支路均为红灯保持3秒后进入下一个状态(计数器清零),否则保持状态
s5: begin
if(cnt >= 4'd3) begin
ns = s0;
cnt_clr = 0;
end
else begin
ns = s5;
cnt_clr = 1;
end
end
endcase
end
end
//描述状态机的输出
always @ (posedge clk_div or negedge rst_n) begin
if(!rst_n) begin
led_0 <= 2'b00;
led_1 <= 2'b00;
blink <= 0;
end
else begin
case(ns)
s0: begin //主路绿灯，支路红灯
led_0 <= 2'b10;
led_1 <= 2'b01;
end
s1: begin
if(!blink) begin //主路绿灯闪烁三秒，支路红灯
led_0 <= 2'b00;
led_1 <= 2'b01;
blink <= 1;
end
else begin
led_0 <= 2'b10;
led_1 <= 2'b01;
blink <= 0;
end
end
s2: begin //主路支路皆是红灯
led_0 <= 2'b01;
led_1 <= 2'b01;
end
s3: begin //主路红灯，支路绿灯
led_0 <= 2'b01;
led_1 <= 2'b10;
end
s4: begin
if(!blink) begin //主路红灯，支路绿灯闪烁3秒
led_0 <= 2'b01;
led_1 <= 2'b00;
end
else begin
led_0 <= 2'b01;
led_1 <= 2'b10;
end
end
s5: begin //主路支路皆是红灯
led_0 <= 2'b01;
led_1 <= 2'b01;
end
endcase
end
end
endmodule
[/source]

怎么用Verilog HDL做一个篮球比赛里的24秒倒计时程序，谢谢

此程序通过STEP的值来选择要控制的电机，3个电机是互不影响的工作，我实在是查不出问题，但是，电机就是没反应，单个电机试过，产生PWM波的程序应该没有问题，各位大神帮我看一下，谢谢啦
`timescale 1ns / 1ps，
module step(
input CLK, //输入时钟
input RST, //输入复位
output[3:0] MOTOR_0, //输出0号电机的PWM波
output[3:0] MOTOR_1, //输出1号电机的PWM波
output[3:0] MOTOR_2 //输出2号电机的PWM波
);
parameter STEP = 4'b0001; //选择电机的控制命令
wire clk;
wire rst;
reg [31:0]cnt;
reg [3:0]phaseout_0;
reg [3:0]phaseout_1;
reg [3:0]phaseout_2;
assign MOTOR_0 = phaseout_0;
assign MOTOR_1 = phaseout_1;
assign MOTOR_2 = phaseout_2;
assign clk = CLK;
assign rst = RST;
/*****************加法器*******************/
always @(posedge clk or posedge rst)
if( !rst ) begin
cnt <= 0;
end
else begin
if(cnt == 32'd50_000_000) begin
cnt <= 0;
end
else begin
cnt <= cnt + 32'd1;
end
end
/***********0号电机的PWM波生成*************/
always @(posedge clk or posedge rst)
if(!rst ) begin
phaseout_0 <= 0;
end
else begin
if(STEP == 4'b0001 || STEP == 4'b0100 || STEP == 4'b0101 || STEP == 4'b0111) begin //判断STEP命令
if(cnt == 26'd50_000_000) begin
phaseout_0 <= 4'b1000;
end
else if(cnt == 26'd37_500_000) begin
phaseout_0 <= 4'b0100;
end
else if(cnt == 26'd25_000_000) begin
phaseout_0 <= 4'b0010;
end
else if(cnt == 26'd12_500_000) begin
phaseout_0 <= 4'b0001;
end
end
end
/***********1号电机的PWM波生成*************/
always @(posedge clk or posedge rst)
if(!rst ) begin
phaseout_1 <= 0;
end
else begin
if(STEP == 4'b0010 || STEP == 4'b0100 || STEP == 4'b0110 || STEP == 4'b0111) begin //判断STEP命令
if(cnt == 26'd50_000_000) begin
phaseout_1 <= 4'b1000;
end
else if(cnt == 26'd37_500_000) begin
phaseout_1 <= 4'b0100;
end
else if(cnt == 26'd25_000_000) begin
phaseout_1 <= 4'b0010;
end
else if(cnt == 26'd12_500_000) begin
phaseout_1 <= 4'b0001;
end
end
end
/***********2号电机的PWM波生成*************/
always @(posedge clk or posedge rst)
if(!rst) begin
phaseout_2 <= 0;
end
else begin
if(STEP == 4'b0011 || STEP == 4'b0101 || STEP == 4'b0110 || STEP == 4'b0111) begin //判断STEP命令
if(cnt == 26'd50_000_000) begin
phaseout_2 <= 4'b1000;
end
else if(cnt == 26'd37_500_000) begin
phaseout_2 <= 4'b0100;
end
else if(cnt == 26'd25_000_000) begin
phaseout_2 <= 4'b0010;
end
else if(cnt == 26'd12_500_000) begin
phaseout_2 <= 4'b0001;
end
end
end
endmodule

新手，请问怎么让一个参数等于0-10随机的数啊，我查了random的用法，但是直接a = ｛$random｝%10；会报错，求解

求倒计时模块 急

对于闹钟 各位大神有什么语句能定住调的时间吗

红色直线是怎么回事？要怎样才能转换为高低电平？F为模块内部信号，是对时钟CLK的分频。请各位大神帮帮忙