verilog编写计数器，用for语句，但是仿真波形不对，求指导

程序：
module aaa(clk, rst, in, out);
input clk, rst, in;
output [2 : 0] out;
reg [2 : 0] out;
reg [2 : 0] a;
always @ ( posedge clk)
begin
if (!rst)
out = 3*d0;
else
if (in)
begin
if (out !== 3*d7)
begin
for (a = 3*d0; a <= 3*d6; a = a + 3*d1)
begin
out = a ;
end
end
else if (out == 3*d7)
begin
out = 3*d0;
end
end
end
endmodule
testbench：
`timescale 1 ns/ 1 ns
module aaa_vlg_tst();
// constants
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg in;
reg rst;
// wires
wire [2:0] out;
// assign statements (if any)
aaa i1 (
// port map - connection between master ports and signals/registers
.clk(clk),
.in(in),
.out(out),
.rst(rst)
);
initial
begin
// code that executes only once
// insert code here --> begin
clk = 0;
forever
#50 clk = ~clk;
// --> end
$display("Running testbench");
end
initial
// optional sensitivity list
// @(event1 or event2 or .... eventn)
begin
// code executes for every event on sensitivity list
// insert code here --> begin
rst = 0;
#100 rst = 1;
@eachvec;
// --> end
end
initial
begin
in = 0;
#150 in = 1;
end
endmodule